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[VHDL-FPGA-Verilog] verilog

Description: verilog设计练习进阶,针对的读者是 verilog hdl的初学者。-Advanced Verilog design practice, in view of the reader is beginner verilog hdl.
Platform: | Size: 103424 | Author: xuping | Hits:

[Software Engineering] Veilogbook

Description: 第一章 数字信号处理、计算、程序、算法和硬线逻辑的基本概念 第二章 Verilog HDL设计方法概述 第三章 Verilog HDL的基本语法 第四章 不同抽象级别的Verilog HDL模型 第五章 基本运算逻辑和它们的Verilog HDL模型 第六章 运算和数据流动控制逻辑 第七章 有限状态机和可综合风格的Verilog HDL-The first chapter of digital signal processing, computing, procedures, algorithms and hard-wired logic of the basic concepts of Chapter II Verilog HDL design methods outlined in Chapter III of the basic Verilog HDL syntax in Chapter IV of different abstraction levels of Verilog HDL model of Chapter V of the basic arithmetic logic and Verilog HDL model of their Chapter VI computing and data flow control logic of Chapter VII of the finite state machine and an integrated style of Verilog HDL
Platform: | Size: 1079296 | Author: 碗筷 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_advanced_digital_design_code_Ch6

Description: VerilogHDL_advanced_digital_design_code_Ch6 Verilog HDL 高级数字设计源码ch6-Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch6Verilog HDL source CH6
Platform: | Size: 69632 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] generic_fifos.tar

Description: Generic FIFO, writen in verilog hdl
Platform: | Size: 12288 | Author: marco | Hits:

[VHDL-FPGA-Verilog] Design_and_Test_VerilogHDL

Description: Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples and has made it clear that it is rare to learn Verilog good information.
Platform: | Size: 1887232 | Author: ZY | Hits:

[VHDL-FPGA-Verilog] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[Com Port] uart2iic

Description: UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-UART to I2C of the Verilog HDL code, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation
Platform: | Size: 3072 | Author: emulous | Hits:

[Com Port] demo_24c01a

Description: 24C01A的Verilog HDL仿真代码，用于I2C接口模块的测试，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-24C01A simulation of Verilog HDL code for the I2C interface module of the test, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation
Platform: | Size: 1024 | Author: emulous | Hits:

[Home Personal application] digtalclk

Description: 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic
Platform: | Size: 2094080 | Author: 张欢 | Hits:

[Other Embeded program] AD7865test1

Description: verilog hdl写的利用fpga控制ad7865进行多路ad数据采集的程序源代码。-err
Platform: | Size: 309248 | Author: nwpu2005 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: 《设计与验证Verilog HDL》光盘内容-err
Platform: | Size: 1003520 | Author: jzhupo | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_trafficlight

Description: 采用Verilog HDL语言编写的交通灯控制系统，这是一个完整的毕设课题，分别有分频、显示译码、倒计时和动态显示驱动模块，实用价值很高，-Using Verilog HDL language of the traffic lights control system, which is a complete set of BI subjects who were frequent, indicating decoding, countdown and dynamic display driver module, a very high practical value,
Platform: | Size: 363520 | Author: 廖耿耿 | Hits:

[Graph program] altera_tft_lcd_controller

Description: Altera 开发环境下的VGA控制源码，Verilog HDL语言编写，支持sopc环境下操作以及驱动-Altera development environment under the control of VGA source, Verilog HDL language to support the SOPC operating conditions, as well as drive
Platform: | Size: 49152 | Author: | Hits:

[VHDL-FPGA-Verilog] simple_MCU

Description: 设计CPU方法及流程！VERILOG hdl-CPU design methods and processes! VERILOG hdl
Platform: | Size: 208896 | Author: 正中 | Hits:

[Other] PCI

Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.-PCI Design Guide The Xilinx LogiCORE PCI interface is a fully verified, pre-implementedPCI Bus interface. This interface is available in 32-bit and 64-bit versions, with support for multiple Xilinx FPGA device families. Itis designed to support both Verilog-HDL and VHDL. The designexamples in this book are provided in Verilog.
Platform: | Size: 899072 | Author: lee | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: VerilogHDL硬件描述语言(简单的Verilog HDL语法-VerilogHDL Hardware Description Language (Verilog HDL simple grammar
Platform: | Size: 4843520 | Author: 张丽滨 | Hits:

[VHDL-FPGA-Verilog] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码-On the dual-port RAM in Verilog HDL source
Platform: | Size: 3072 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: cordic算法的Verilog HDL具体实现-CORDIC algorithm specific realize Verilog HDL
Platform: | Size: 7168 | Author: 王伟 | Hits:

[SCM] LCD_Driver

Description: LCD的驱动程序　用verilog HDL 编写　可以用于FPGA上　经过测试　可以使用-LCD driver with verilog HDL can be used for the preparation of the FPGA can be tested using
Platform: | Size: 2048 | Author: 德刚 | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:
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